Aldec Accelerates Assertion-Based Verification By 10-50X

Henderson, Nevada -- May 9, 2003 - Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced today the availability of the industry's fastest hardware acceleration platform. Riviera-IPT is a unified, assertion-based hardware acceleration platform that maximizes simulation performance and accelerates ASIC and FPGA design verification by 10x - 50x over traditional methods. Because it is based on Aldec's industry-proven VHDL and Verilog common kernel mixed-language simulator and hardware acceleration technology, Riviera-IPT is ideal for the newest devices made in 180nm technology and below and for multi-million gate system-on-chip designs. Riviera-IPT will be demonstrated beginning June 2 at the Design Automation Conference in Aldec's booth #1024.

"Using assertions in the verification process saves customers a tremendous amount of time," said Eric Seabrook, product marketing manager for Aldec. "For larger, system-level designs, it has also become important to provide designers with a unified acceleration platform for superior efficiency. With Riviera-IPT, our customers get VHDL, Verilog, assertion-based verification, SystemC and hardware acceleration in one seamless platform."

Assertion-Based Verification
Riviera-IPT enhances debugging capabilities and accelerates the verification process by supporting assertions in both a software and hardware environment. The high-level language of assertions contains powerful declarative constructs for capturing and verifying design specifications throughout the design cycle. Additionally, using assertions in conjunction with a traditional testbench produces faster verification results and improves the overall coverage with less effort. Assertions are portable and can be added to the design outside the Unit Under Test (UUT) or can be embedded directly in the design during coding with Riviera-IPT. Adding assertions to a design block will speed its verification, particularly if it contains complex algorithms and millions of gates.

Accelerating Assertions in Hardware
In addition to handling assertions in software, Riviera-IPT has the unique ability to compile assertions into hardware, along with selected design sections. The assertion compiler in Riviera-IPT can produce module checkers in the form of RTL code added to the synthesizable portion of the design. Riviera-IPT can then utilize these assertion checks at both the behavioral (dynamic) level in the software simulator, and at the structural (static) level in the hardware accelerator. The hardware-based assertion monitors consist of two principal parts: logical sequence of signals to be observed and the desired response when the assertion violation is detected. Once implemented and verified, assertions can remain as part of the final design and be used as real time protocol checkers and detect violations during normal device operation. The user can choose to compile the assertion checkers into hardware and gain extra productivity during design prototyping. These checkers can also be used later on for monitoring the final product operation.

Complete Verification Platform
Riviera-IPT's common kernel architecture supports VHDL, Verilog, SystemC, assertions and acceleration. It also handles memories and devices such as DSPs and ASICs for joint verification of legacy designs, EDIF-based IP cores, existing hardware, and HDL blocks. By eliminating potential conflicts between verification tools, teams and design methods, Riviera-IPT is able to accelerate design verification by 10x-50x. Designers in turn save time and produce more reliable tapeouts. Riviera-IPT enables designers to verify and optimize their designs in smaller-sized, more manageable blocks. Each block is verified in software by Riviera-IPT's built-in, event-driven simulator to allow for total visibility and debugging of the module before it is synthesized and placed in the hardware accelerator.

After the verified module is placed in the hardware board, it remains "connected" to the remainder of the design residing in the software simulator, but eliminates the typical processing overhead. Ultimately, the majority of the design blocks, including assertions, reside in hardware, while the behavioral testbench and SystemC components remain in software.

The interface between the components in hardware and software is managed through Riviera-IPT's Design Verification Manager (DVM), which facilitates the entire process and provides communication between the software and hardware components.

System Configuration
Based on Aldec's industry-proven mixed HDL verification environment, Riviera-IPT includes an IEEE VHDL, Verilog and EDIF common kernel simulator, the Design Verification Manager (DVM), a hardware accelerator board with a capacity of up to 12 million FPGA gates, and an interface to a SystemC compiler. Optionally, Synplicity's Synplify™ logic synthesis may be added to complete the design flow. The Riviera-IPT system can be configured for UNIX, Linux or Windows NT/2000/XP. Riviera-IPT will accommodate up to 12 million FPGA gates or 3 million ASIC gates.

Availability
Riviera-IPT is available today. Riviera-IPT is sold directly by Aldec in the U.S. and authorized international distributors. For additional information about Riviera-IPT contact Aldec at 702-990-4400 or visit www.aldec.com

About Aldec
Aldec, Inc., a 19-year-old EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers' needs with its offices located around the globe. Continuous innovation, superior product quality and total commitment to customer service comprise the foundation of Aldec's strategic objectives. The company is headquartered in Henderson, Nevada and has sales offices and distributors throughout the world. Additional information about Aldec is available at http://www.aldec.com.

Contact:

Eric Seabrook
Aldec, Inc.
(702) 990-4400 ext. 224
erics@aldec.com

Wendy Truax
HighPointe Communications
503-672-9073
wendy@hipcom.com